GMS30C7201 Datasheet, PDF (247/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO time-out interrupts occurs
as follows:
1 A FIFO time-out interrupt occurs if the following conditions exist:
- at least one character is in the FIFO
- the most recent serial character received was longer than four continuous
character times ago (if two stop bits are programmed, the second one is included
in this time delay)
- the most recent CPU read of the FIFO was longer than four continuous character
times ago
This will cause a maximum character received to interrupt issued delay of 160 ms at
300 baud with a 12-bit character.
2 Character times are calculated by using the RCLK input, which is the internal signal
of UART for a clock signal (this makes the delay proportional to the baud rate).
3 When a time-out interrupt has occurred, it is cleared and the timer is reset when the
CPU reads one character from the RCVR FIFO.
4 When a time-out interrupt has not occurred the time-out timer is reset after a new
character is received or after the CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled (FCR 0 = 1, IER 1 = 1), XMIT
interrupts occurs as follows:
1 The transmitter holding register interrupt (02) occurs when the XMIT FIFO is empty.
It is cleared as soon as the transmitter holding register is written to (1 to 16 characters
may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read.
2 The transmitter FIFO empty indications will be delayed 1 character time minus the last
stop bit time whenever the following occurs: THRE = 1 and there has not been at least
two bytes at the same time in the transmit FIFO since the last THRE = 1. The first
transmitter interrupt affect changing FCR0 will be immediate if it is enabled.
Character time-out and RCVR FIFO trigger level interrupts have the same priority as the current
received data available interrupt; XMIT FIFO empty has the same priority as the current
transmitter holding register empty interrupt.
Test Registers of Uart
Four extra registers are provided inside the UART for test purposes. They are memory mapped
as shown in Table 13-11: UART test registers.
Registers
Base Address + 0x20
Base Address + 0x30
Base Address + 0x34
Base Address + 0x3C
Read
UartEN
UartTOR
Write
UartEN
UartTIR
UartTICCLK
Width
1-bit
7-bit. Write-only.
3-bit. Read-only.
Dummy address for generating TIC
Clock. Write-only.
Table 13-11: UART test registers
Note
These registers should only be used for test purposes, and should not be accessed during normal
operation.
Detailed descriptions for each of the four registers now follow.
GMS30C7201 Data Sheet
13-19