GMS30C7201 Datasheet, PDF (188/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
or more ones are detected, a receiver abort occurs. Note that data is moved from the serial shifter
to the temporary buffer a byte at a time, and seven consecutive ones may bridge two bytes. For
this reason, after an abort is detected, the remaining data in the serial shifter is discarded along
with the most recent byte of data placed in the temporary buffer. After this data is discarded, the
oldest byte of data in the temporary buffer is placed in the receive buffer, the EOF tag is set
within the top entry of the buffer (next to the byte transferred from the temporary buffer), the
receiver abort interrupt is signalled, and the receiver logic enters hunt mode until it recognizes
the next flag.
If the user disables the receiver during operation, reception of the current data byte is stopped
immediately, the serial shifter and receive buffer are cleared, and all clocks used by the receive
logic are automatically shut off to conserve power.
Transmit Operation
The user may either “prime” the transmit buffer by filling it with data or allow service requests
to cause the DMA to fill the buffer once the MIr transmitter is enabled. Once enabled, the
transmit logic issues a service request if its buffer is empty. A Serial Infrared Interaction Pulse
(SIP) is transmitted in order to guarantee non-disruptive co-existence with slower (up to
115.2Kb/s) systems, for example another GMS30C7201 device attempting to use its SIr. This
is followed by continuous transmission of flags until valid data resides within the buffer. Once
a byte of data resides at the bottom of the transmit buffer, it is transferred to the serial shifter, is
encoded and shifted out onto the transmit pin clocked by the programmed baud rate clock. Note
that the flag and CRC value are automatically transmitted and need not be placed in the transmit
buffer.
When the transmit buffer is emptied, an interrupt and/or DMA service request is signalled. If
new data is not supplied soon enough, the buffer is completely emptied and the transmit logic
attempts to take additional data from the empty buffer, one of two actions can be taken as
programmed by the user. An underrun can either signal the normal completion of a frame or an
unexpected termination of a frame in progress.
When normal frame completion is selected and an underrun occurs, the transmit logic transmits
the 16-bit CRC value calculated during the transmission of all data within the frame (including
the address and control bytes), followed by a flag to denote the end of the frame. The transmitter
then transmits an SIP, followed by a continuous transmission of flags until data is once again
available within the buffer. Once data is available, the transmitter begins transmission of the
next frame.
When unexpected frame termination is selected and an underrun occurs, the transmit logic
outputs an abort and interrupts the CPU. An abort continues to be transmitted until data is once
again available in the transmit buffer. The MIr then transmits an SIP, followed by a double flag
and starts the new frame. The off-chip receiver may choose to ignore the abort and continue to
receive data, or to signal the serial port to retry transmission of the aborted frame.
If the user disables the transmitter during operation, transmission of the current data byte is
stopped immediately, the serial shifter and transmit buffer are cleared, and all clocks used by the
transmit logic are automatically shut off to conserve power.
CPU and DMA Register Access Sizes
Bit positioning, byte ordering and addressing of the MIr are described in terms of little endian
ordering. All MIr control and status registers are 8-bits wide and are located in the least
significant byte of individual words. Transmit and receive data buffers are 32 bits wide, with the
first byte to be transmitted/ or received located in the least significant byte position. The ARM
peripheral bus does not support byte or half-word operations. All reads and writes of the MIr by
the CPU should be word wide. Separate DMA requests exist for the transmit and the receive
buffer. If the DMA controller is used to service the transmit and/or receive buffers, the user must
ensure the DMA is properly configured to perform single word-wide accesses. Burst mode
DMA is not supported by the peripheral. Refer to Table 12-34: Ir Interface Block Registers
and their Physical Addresses on page 12-51 for a summary of the MIr serial port’s registers.
12-34
GMS30C7201 Data Sheet