GMS30C7201 Datasheet, PDF (147/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.11 LCD Controller Status/Mask and Interrupt Registers
The LCD controller status, mask and interrupt registers all have the same format. Each bit of the
status register is a status bit that may generate an interrupt. These are masked by the
corresponding bits in the mask register. The interrupt register is the logical AND of the status
and mask registers, and the interrupt output from the LCD controller is the logical OR of the bits
within the interrupt register.
The LCD controller status register (LCSR) contains bits that signal an under-run error for the
FIFO, the DMA next base update ready status, and the DMA done status. Each of these
hardware-detected events can generate an interrupt request to the interrupt controller.
11.11.1 LCD Frame Done (LDone)
The LCD Frame Done (Done) is a read-only status bit that is set after the LCD has been disabled
and the frame that is active finishes being output to the LCD’s data pins. It is cleared by writing
the base address (LcdDBAR) or enabling the LCD, or, by writing “1” to the LDone bit of the
Status Register. When the LCD is disabled by clearing the LCD enable bit (LcdEn=0) in
LcdControl, the LCD allows the current frame to complete before it is disabled. After the last
set of pixels is clocked out onto the LCD’s data pins by the pixel clock, the LCD is disabled and
Done is set.
11.11.2 LCD Next Frame (LNext)
The LCD Next Frame (LNext) is a read-only status bit that is set after the contents of the LCD
DMA base address register are transferred to the LCD DMA current address register, and it is
cleared when the LCD DMA base address register is written.
11.11.3 FIFO Underflow Status (LFUF)
The LCD FIFO underflow status (LFUF) status bit is set when the LCD FIFO under-runs. The
status bit is “sticky”, meaning it remains set after the FIFO is no longer under-running. The
status bit is cleared by writing a ‘1’ to this bit of the status register.
Bit Name
Description
0
LFUF
FIFO underflow status/mask/interrupt bit
1
LNext
LCD Next base address update status/mask/interrupt bit
This status bit is set when the base address is transferred to the current
address register at the start of frame
2
VComp Vertical compare interrupt
3
LDone
LCD Done frame status/mask/interrupt bit
This status bit is set when LcdEn has been set to ‘0’, after the current frame
completes
Table 11-11: LCD Controller Status/Mask and Interrupt Registers
11.11.4 VComp Interrupt
This bit is set when the Lcd timing generator reaches the vertical region programmed in the
Video Control Register. This bit is “sticky”, meaning it remains set until it is cleared by writing
a “1” to this bit of the status register.
11.11.5 VGA Status/Mask/Interrupt registers
The VGA status, mask and interrupt registers are exactly the same format as the LCD registers.
The only difference is that if the VGA is disabled, it is disabled immediately, rather than waiting
for the end of frame. This means there is no equivalent of LDone for the VGA
GMS30C7201 Data Sheet
11-19