GMS30C7201 Datasheet, PDF (285/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
Name
PD[31:0]
PSTB
PWRITE
PSEL
UARTRING
Type
InOut
In
In
In
Out
Source/
Destination
APB Peripherals, BD
APB Bridge
APB Bridge
APB Bridge
UART
Description
This is part of the bidirectional peripheral data bus. The
data bus is driven by this block during read cycles (when
PWRITE is LOW).
This strobe signal is used to time all accesses on the
peripheral bus. The falling edge of PSTB is coincident
with the falling edge of BCLK (ASB system clock).
When HIGH, this signal indicates a write to a peripheral,
and when LOW, a read from a peripheral.
This signal has the same timing as the peripheral address
bus. It becomes valid before PSTB goes HIGH and
remains valid after PSTB goes LOW.
When HIGH, this signal indicates the AFE module has
been selected by the APB bridge. This selection is a
decode of the system address bus (ASB). For more
details see AMBA Peripheral Bus Controller (ARM DDI
0044).
Ring detect signal to UART.
Table 13-38: Signal descriptions
Name
nCON
RING
RLY
SDI
SDO
SDFS
SCLK
INTAFE
Type
Out
In
Out
In
Out
In
In
Out
Source/
Destination
CODEC
DAA
DAA
CODEC
CODEC
CODEC
CODEC
Interrupt Controller
Description
Serial control/data input select (control at LOW).
Ringing signal input.
Relay control output.
Serial data input/ Control data input.
Serial data output. Active when TREN bit is set,
otherwise held LOW.
Serial data frame synchronous signal input.
Serial data clock input at a frequency of 864kHz.
AFE Interrupt. Active HIGH.
Table 13-39: Specific block signal descriptions
13.9.3 Functional Description
The AFE interface is a serial-to-parallel and parallel-to-serial converter providing full duplex
transmission with an external serial AFE(CODEC). Two 32-byte FIFOs are provided to help
optimize processor usage. Data is clocked in and out of the block with the SCLK signal which
runs at 864kHz.
GMS30C7201 Data Sheet
13-57