GMS30C7201 Datasheet, PDF (87/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

SDRAM Controller
8.7 AMBA Accesses and Arbitration
The SDRAM controller bridges both the AMBA Main and Video buses. On the Main bus, the
SDRAM appears as a normal slave device. On the Video DMA bus, the SDRAM controller
integrates the functions of the bus arbiter and address decoder.
Writes from the main bus may be merged in the quad word merging write buffer. See 8.8
Merging Write Buffer on page 8-17 for more information on this feature.
Access requests from either the Main or Video buses are arbitrated by a Main/Video arbiter
according to the following sequence:
Highest Priority: LCD/VGA (modified round robin)
Refresh request
Lowest Priority:
Main bus peripheral (PMU, ARM, Piccolo, DMA)—order
determined by Main bus arbiter.
The LCD and VGA have nominally the same priority, and are arbitrated using a “biased round
robin” algorithm. The “biased round robin” algorithm in this context means that if both of the
video peripherals on the video bus request access at the same time, the video system indicated
by the P bit in the control register gets first access, then the video system not selected by the P
bit is granted access, regardless of whether the system selected by the P bit is still requesting
access. As an example, if the P bit is 1, the VGA is given priority, so if both VGA and LCD
request access at the same time, VGA is granted first, then LCD, even if VGA is still requesting
after its first access.
LCD and VGA SDRAM accesses always occur in bursts of 16 words. Once a burst has started,
data is presented by the SDRAM controller without wait states. The LCD and VGA may only
read data from SDRAM, no write path is supported.
If a refresh cycle is requested, then it will have lower priority than either the VGA or LCD, but
will be higher than any other accesses from the Main bus. Assuming a worst case BCLK
frequency of 8MHz, the maximum, worst case latency that the arbitration scheme enforces is
11.5µs before a refresh cycle can take place. This is comfortably within the 16µs limit. Note
that the four external SDRAM devices are refreshed on four consecutive clock cycles to reduce
the peak current demand on the power source.
The arbitration of the Main bus is left to the Main bus arbiter.
Data transfers requested from the Main bus always occur as a burst of eight half-word accesses
to SDRAM. Access requests from the Main bus cannot be broken into by the Main bus arbiter.
In the case where fewer than four words are actually requested by the Main bus peripheral, the
excess data from the SDRAM is ignored by the SDRAM controller in the case of read
operations, or masked in the case of writes.
In the case where more than four words are actually requested by the Main bus peripheral, the
SDRAM controller asserts MBLAST to force the ASB decoder to break the burst.
In the case of word misalignment to a quad word boundary (when any of address bits [3:0] are
non-zero at the start of the transfer), MBLAST is asserted at the next quad word boundary (bits
2 and 3 set) to force the ASB decoder to break the burst.
Sequential half word (or byte) reads are not supported. Any burst requests for byte or half word
reads are broken by the SDRAM controller asserting BLAST.
This is not an issue, since although the GMS30C7201 includes the THUMB processor, which
can generate sequential half word accesses, if the cache is enabled, these will become quad word
cache line fills.
In the case of quad word misalignment, byte or half word access requests from the Main AMBA
bus, the data requested by address bits MBA[3:2] is accessed from the SDRAM first.
In the case of byte or half word reads, data is replicated across the whole of the ASB data bus.
GMS30C7201 Data Sheet
8-15