GMS30C7201 Datasheet, PDF (298/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Slow AMBA Peripherals
13.11.3AIC Unit hardware interface and signal description
Name
PCLK
BnRES
ACLK
PA[7:2]
PD[31:0]
PSTB
PWRITE
PSEL
INTAIC
AA[3:0]
AD[7:0]
AASN
AWRn
ARDn
AIOSTOP
ATEST
CALTEST
DATA
Type
In
In
Out
In
InOut
In
In
In
Out
Out
InOut
Out
Out
Out
Out
Out
Out
In
Source/
Destination
UART Clock
APB Bridge
AIC unit/ADC
APB Bridge
APB Peripherals,
BD Bus
APB Bridge
APB Bridge
APB Bridge
Interrupt Controller
AD Converter
AD Converter, AIC
AD Converter
AD Converter
AD Converter
AD Converter
AD Converter
AD Converter
AD Converter
Description
UART clock.
Reset signal generated from the APB Bridge.
ADC operation clock output (PCLK or test clk).
This is the peripheral address bus, which is used by an individual
peripheral for decoding register accesses to that peripheral.
The addresses become valid before PSTB goes HIGH, and remain
valid after PSTB goes LOW.
This is the bi-directional peripheral data bus. The data bus is driven
by this block during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of
BCLK.
When HIGH, this signal indicates a write to a peripheral. When
LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes HIGH and remains valid after
PSTB goes LOW.
When HIGH, this signal indicates that this module has been selected
by the APB bridge. This selection is a decode of the system address
bus (ASB). For more details, see AMBA Peripheral Bus Controller
(ARM DDI0044).
Interrupt request when either touch panel buffer is full, or sound
buffer is full, or battery data is checked.
This is the address bus used to select a register in the ADC unit.
This is a the bi-directional data bus which is connected to the ADC.
Address strobe signal for accessing ADC registers. When there is a
signal transition to a LOW state, address is valid.
Write strobe signal to write control or status register of ADC. This is
an active LOW signal.
Read strobe signal to read the contents of ADC registers. This is an
active LOW signal.
This signal is used to stop input/output operation of the ADC. When
this signal becomes HIGH (1), all ADC operations will stop, to save
power to the ADC drive.
ADC test signal. This signal has the value of 0 in normal mode.
ADC test signal. This signal has the value of 0 in normal mode.
ADC test signal.
Table 13-54: AIC signal descriptions
13-70
GMS30C7201 Data Sheet