GMS30C7201 Datasheet, PDF (225/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
Data Register (SDADR)
This register can be programmed after setting Bit 5 of the SCONT register.
Bit
31 (MSB)
Initial Value
32’b0
30 (data)
:
:
1 (data)
0 (LSB)
Description
Sound Data
This register receives data by DMA
Controller or CPU. This unit processes the
lower 16-bit data followed by the higher 16-
bit data. After the lower 16-bit is processed,
this unit is ready to receive new data and
sends a request signal to DMA Controller or
CPU. In mono mode, the lower byte is
processed first followed by the higher byte.
Table 12-46: SDADR bit description
Test Output Register (STOR)—programmable register
This register is used for the operation of DAC. This register should only be used for DAC test
purposes, and should not be accessed during normal operation.
Bit
Initial Value
Description
17
0
When set, TICCLK is used as clock source instead of normal
clock input during production test:
0 - normal mode
1 - TICCLK mode
16
0
Only if set, the values of bit 15 and bit 14 replace the original
Soundclk and Dapulse signal. Used only for test
purposes.
0 - normal mode
1 - test mode
15
0
Soundclk signal input - see Note 1.
When bit 16 is set, this bit is meaningful. The Soundclk
signal is changed by the value of this bit.
14
0
Dapulse signal input - see Note 2.
When bit 16 is set, this bit is meaningful. The Dapulse
signal is changed by the value of this bit.
13
0
Ticdac mode for DAC test. In this mode, PCLK is changed
by TICCLK register:
0 - normal mode
1 - Ticdac mode
Table 12-47: Test Output Register (STOR)—programmable register
GMS30C7201 Data Sheet
12-71