GMS30C7201 Datasheet, PDF (105/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PCMCIA Interface
System
5V
Power
3.3V
Supply
12V
External
BUS ^B_D[15:0]
Interface _{B_A[25:0]}
EBI Control Signals
nVCC_5EN_SKT1, nVCC_5EN_SKT2,
nVCC_3EN_SKT1, nVCC_3EN_SKT2,
VPP_EN1_SKT1, VPP_EN1_SKT12
VPP_EN2_SKT1, VPP_EN2_SKT12
CaDRV
CbDRV
PCMCIAOutEn0
PCMCIA Wait_SKT1
Wait_SKT2
Card ^Reset_SKT1
Reset_SKT2
Controller
nREG,
nOE, nWE
nCIORD, nCIOWD
nCD2, nCD1, VS2, VS1,
BVD2, BVD1, WP, RDY/nBSY : SKT1
nCD2, nCD1, VS2, VS1,
BVD2, BVD1, WP, RDY/nBSY : SKT2
MIC2653A
(Power
Control^{VCC 3.3Vor 5V}
Chip) ^12V
5V tolerant Buffer
LCX16245
(16-Bit Buffer)
-Bidirectional
5V tolerant Buffer
LCX16244
(16-Bit Buffer)
-Unidirectional
VCC,
VPP1
VPP2
nREG,
nOE, nWE
nCIORD, nCIOWD
Data[15:0] _SLOT1
Addr[25:0]
Wait
Reset
nCD2, nCD1, VS2, VS1,
BVD2, BVD1, WP, RDY/nBSY
5V tolerant Buffer
LCX16244
(16-Bit Buffer)
-Unidirectional
VCC,
VPP1
VPP2
nREG,
nOE, nWE
nCIORD, nCIOWD
Data[15:0] ^SLOT2
Addr[25:0]
Wait
Reset
nCD2, nCD1, VS2, VS1,
BVD2, BVD1, WP, RDY/nBSY
* All data line must be pull-downed with 100K register
*CD2, CD1, VS2, VS1: Pull-upedwithSystemPower
* Other Status Pins : Pull-uped with Card Power
Figure 10-3: External Circuit Diagram
This diagram describes the external floorplan for PCMCIA and the interconnection from the
view of system level. This diagram also describes the pin connection with the socket and the
controller.
10.1.1 Hardware interface and signal description
10.1.2 Host Bus interface signal
The signals listed below go to the PCMCIA Interface on the ASB side.
Name
BCLK
BA[28:21]
Type
Input
Input
Source
Clock
Controller
ASB
Description
System Bus Clock
This Clock times all bus transfers.
System Bus Address
Table 10-1: Host Bus Interface Signals
GMS30C7201 Data Sheet
10-5