GMS30C7201 Datasheet, PDF (106/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

PCMCIA Interface
Name
BA[6:2]
Type
InOut
BA[0]
Input
BD[7:0]
Input
nBRES
BWRITE
Input
Input
BERROR
Output
BLAST
BWAIT
Output
Output
BSIZE[1:0]
Input
DSELPCM
Input
DSELREG
Input
Source
Description
ASB
Upper three bits are required to address
translation and lower four bits to configure
control register
ASB
Upper three-bits are required to address
translation and lower four bits to configure
control register
ASB
System Data Bus
These bits are used to configure the control
register. All configuration registers are eight
bits wide.
ASB
This signal indicates the reset status of the
AMBA ASB
ASB
When HIGH, this signal indicates a write
transfer and when LOW, a read.This signal has
the same timing as the address bus
ASB
This slave response is driven HIGH during
phase one of BCLK when a transfer error has
occurred. When LOW the transfer is
successful
ASB
This slave response is driven HIGH during
phase one of BCLK when PCMCIA Host Bus
Adapter is selected.
ASB
This slave response is driven HIGH during
phase one of BCLK when PCMCIA Host Bus
Adapter is selected and is used to indicate if
the PC Card has completed its current transfer.
The signal is driven low at the end of the cycle.
ASB
This signal indicates the size of the transfer
which may be byte, half-word or word. When
HIGH, this signal indicates that one of the
configuration registers is selected.
AMBA
Decoder
This signal changes in phase two of BCLK.
When HIGH, this signal indicates that one of
the configuration registers is selected.
AMBA
Decoder
This signal changes in phase two of BCLK.
Table 10-1: Host Bus Interface Signals (Continued)
10-6
GMS30C7201 Data Sheet