GMS30C7201 Datasheet, PDF (178/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
12.3.7 Ir Data Tail Register
The Ir Data Tail Register (IrDataTail) is a 24-bit write-only register used for transmitting frames
whose payload data is not an integral multiple of four bytes long.
IrDataTail may be written to using one of three addresses. Bits two and three of the address
determine how many bytes within the word written are significant, i.e. are intended for
transmission. If none of these addresses is written to the register remains marked as empty and
payload data will be read by transmit logic from the 32-bit FIFO only. The status of this register
does not affect the TFS flag, nor does it cause interrupts or DMA requests to be generated.
Address
Bytes to be transmitted
Bits
0h80011014
least significant byte in word only
bits 0–7
0h80011018
least significant two bytes in word only
bits 0–15
0h8001101C
least significant three bytes in data word
bits 0–23
Table 12-27: Data Tail Register addresses and bytes to be transmitted
Data is removed from this register by the transmit logic once the main transmit FIFO (IrData)
is empty. Provided that the transmit FIFO does not underrun prematurely, data from this register
will form the last data bytes in a frame. The transmit logic will only begin to terminate a frame
-- using either a CRC or abort sequence -- once both the transmit FIFO and the IrDataTail
register are empty.
Figure 12-6: Bit locations within the Ir Data Tail Register The tail register is cleared whenever
it is read by the transmit logic or the TXE bit in IrCon is cleared.
Address:: 0h8001 1014 ... 0h8001 101C
Bit 23
byte 2
byte 1
IrDataTail
byte 0
Write Only
Bit 0
Figure 12-6: Bit locations within the Ir Data Tail Register
12-24
GMS30C7201 Data Sheet