GMS30C7201 Datasheet, PDF (132/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

LCD & VGA Controllers
11.2.2 VGA control
11.2.3 LCD datapath
Palette RAM, and 16bpp mode
Logical pixels are either 4, 8 or 16 bits. In 4- and 8-bit modes, the logical pixel value is used to
index into the three palette arrays to select the three color components of the physical pixel
value. In 16-bit pseudo true-color mode, a patented technique is used to allow 2¹⁶ colors to be
selected from 2²⁴ possible colors. Separate color gun values are independently used to index
into the three palette arrays, to select an 8-bit value for each of the color guns. By splitting the
palette RAM into three separate RAM arrays, it allows 16-bit mode to generate 8-bit color gun
data. The method used is an ARM patented technique, where 16bpp data is split into three over-
lapping 8-bit fields that are used to index into the three RAM arrays. The red gun is indexed by
bits 15:8 of the 16-bit pixel value, the blue gun is indexed by bits 7:0 of the pixel value, and the
green gun is indexed by bits 11:4 of the pixel value. By programming the palette with the correct
values, 5:5:5, 5:6:5, 4:8:4, and many other combinations of 16-bit data may be used. Thus:
4 bpp
16 palette entries are used for each palette array. All three palette RAMs are
indexed by pixel[3:0]
8 bpp
256 palette entries are used for each palette array. All three palette RAMs are
indexed by pixel[7:0]
16 bpp
256 palette entries are used for each palette array. Red array is indexed by
pixel[15:8], green array is indexed by pixel[11:4], and blue array is indexed
by pixel[7:0]
The control logic for the VGA block consists of 3 main blocks.
• a video timing generator block
This divides down the pixel clock from the video PLL and produces the timing control
signals (VSync, HSync, whether it is video data or border color to be displayed) for
the monitor and video DACs.
• a DMA bus control block
This generates the DMA address for the SDRAM controller and generates the DMA
request signal to the SDRAM controller, and controls receiving the DMA data, and
writing it into the VGA FIFO.
• a register slave interface
This resides on the fast peripheral bus and allows registers to be written from the
processor. The registers and palette are fast peripheral bus slaves.
The LCD and VGA palettes have separate address spaces for reads and writes. However, there
is also a combined address space for palette writes. Writing to this area causes both the LCD
and the VGA palettes to be updated with the same data. When this option is used, 4 bits of each
LCD color gun value are thrown away, so that the 8 bits per gun of the VGA palette data can be
used to program the LCD palette. Thus the LCD gets the MS 4 bits of each VGA gun data. The
LCD palette write is organized such that it used the same format for writes from the CPU as the
VGA palette data, with it discarding the LS 4 bits of each gun data.
The LCD data path is similar to the VGA data path, but it has a few additions. In TFT mode, it
is similar to VGA, except that the digital RGB data is output directly to the pins of the chip,
without going via a video DAC. However, in STN mode, the data must be grayscaled, and then
formatted for the LCD panel. The grayscaler block converts the 4 bit per color gun data into a
single bit per gun, using a patented time/space dither algorithm. In mono mode, only the B gun
data is used. The output of the grayscaler is fed to the formatter, which formats the pixels in the
correct order for the LCD panel type in use. (4 or 8 mono pixels per clock for mono panels, or
2²/₃pixels per clock for color data.) The output of the formatter in color mode is bursty, due to
the 2²/₃pixels per clock that are output, so the formatter output goes to a small FIFO, which
smooths out this burstiness, before data is output to the LCD panel at a constant rate.
11-4
GMS30C7201 Data Sheet