GMS30C7201 Datasheet, PDF (279/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

CS
XCHMODE
TestMode
LOOP
SPIEN
XCH
SPISR register
Slow AMBA Peripherals
This bit is Chip select signal. In order to communicate external
device(MMC), CP asserts 0 in this bit.
0 = when CP can exchange data with external device (MMC)
1 = when CP cannot exchange data with external device (MMC)
This bit determines the direction of transfer
0 = when CP have valid data to send to MMC (send mode)
1 = when CP have valid data to receive from MMC (receive mode)
When TestMode bit is set, SPI-MMC block is in TIC mode. When
Tic mode, the operation of the SPI-MMC is same in normal mode
except that Clock source is not PCLK but TCLK which is made in
the block.
0 = Normal operation
1 = The SPI-MMC block is in TIC mode
When set, this bit selects the local loopback operation. The
transmitter output is internally connected to the receiver input.
When in loopback mode, the operation of SPI-MMC block is same
in normal mode except MISO is internally connected MOSI.
0 = Normal operation
1 = The SPI-MMC block is in loopback mode
This bit enables the SPIMMC. The enable should be asserted before
initiating an exchange and should be negated after the exchange is
complete. When the SPIEN bit is cleared, consumes minimal power.
0 = SPI master disable
1 = SPI master enable
This bit triggers the state machine to generate clocks at the selected
bit rate.
1 = Initiate exchange
0 = No exchange occurs
7
6
5
4
0
TX empty XCHDONE Rx full
Reserved
TX empty
XCHDONE
This bit is set when TX data buffer is empty. If TX empty goes
HIGH, a serial peripheral interrupt is generated. Clearing the TX
empty bit is accomplished by reading the SPISR.
This bit is set when exchange is completed between CP and MMC.
If XCHDONE bit goes HIGH, a serial peripheral interrupt is
generated. Clearing the XCHDONE bit is accomplished by reading
the SPISR.
GMS30C7201 Data Sheet
13-51