GMS30C7201 Datasheet, PDF (181/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

Fast AMBA Peripherals
stored in the IrDataTail register are transmitted before the Ir encoder sends the CRC and end of
frame flags.There are three distinct addresses to write the end of frame data to. The addresses
are given in Table 12-29: Addresses for end of frame data below. This allows a single word
write to specify the data to be transmitted and the number of trailing bytes to send.
Bytes to transmit
Address to write to
1
0x80011014
2
0x80011018
3
0x8001101C
Table 12-29: Addresses for end of frame data
If there is a single byte to transmit, write to address 0x80011014, for two bytes write to
0x80011018 and if there are three trailing bytes write to 0x8001101C.
Starting Transmission
Set IrCon.TXE Transmit enable bit.
12.5.3 End of Frame
End of Buffer Interrupt from DMA
DMAFLAGR.FLAG1 will be set when the number of words specified when initializing the
DMA transfer length. This can be checked in an Interrupt Service Routine and cleared by
writing a 1 to this bit.When this interrupt has occurred, all remaining data to transmit is either
in the FIFO or in the IrDataTail register. At this point, clearing the TUS bit in the IrCon register
will ensure that when transmission is complete the CRC and end of frame flags are transmitted.
Disable Transmit Circuitry
To save power, after completion of the frame transmission, clear the Transmit Enable (TXE) bit
in the IrEnable register.
12.5.4 Error conditions
Transmit buffer Underrun
This is only signalled if IrCon register bit TUS is set to 1 as described in Select Transmit
Underrun Action on page 12-26.
GMS30C7201 Data Sheet
12-27