GMS30C7201 Datasheet, PDF (75/352 Pages) Hynix Semiconductor – 60MHz operation frequency Low power consumption

8.2 Features
SDRAM Controller
Clock Speed
External Bus interface
Memory
Programmable Auto Refresh
Timer
60MHz
100MHz
(0.35µm process)
(0.25µm process)
16 bits wide (two accesses required for each word).
2–64 Mbytes in up to four devices. The size of each
memory device may be different. Programmable
CAS delays of 1, 2 or 3. Supports SDRAMs
organized with either two or four banks with page
lengths of 256 or 512 half words. Note that the
SDRAMs should be of the same speed grade.
Allows correct operation with large range of system
clock frequencies.
Video Resolution
LCD 640 x 240
LCD 640 x 240
VGA 640 x 480
VGA 800 x 600
Video
Bandwidth
Mbyte/sec
15
47
40
ARM Bandwidth
(video active)
Mbyte/sec
31.5
16
ARM Bandwidth
(video inactive)
Mbyte/sec
39.2
39.2
ARM Bandwidth
(average) Mbyte/
sec
32.7
22.5
20
39.2
25.4
Table 8-1: 60MHz operation
Video Resolution
LCD 640 x 240
LCD 640 x 240
VGA 640 x 480
VGA 800 x 600
LCD 640 x 480
VGA 640 x 480
Video
Bandwidth
Mbyte/sec
15
47
40
64
ARM Bandwidth
(video active)
Mbyte/sec
48.8
23.6
ARM Bandwidth
(video inactive)
Mbyte/sec
57
57
ARM Bandwidth
(average) Mbyte/
sec
50
32
29.2
57
37
12.5
57
25
Table 8-2: 100MHz operation
Note
The above timings represent the worst case timing. Best case timings are at least 25% better.
Worst case timings assume that all accesses are from different pages in banks that are already
open, and that no pipelining occurs between Video and ASB accesses.
GMS30C7201 Data Sheet
8-3