MC912D60ACPVE8 Datasheet, PDF (99/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Flash Memory
Flash EEPROM Registers
7.6 Flash EEPROM Registers
FEE32LCK/FEE28LCK — Flash EEPROM Lock Control Register
Bit 7
6
5
4
3
2
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
$00F4/$00F8
1
Bit 0
0
LOCK
0
0
In normal modes the LOCK bit can only be written once after reset.
LOCK — Lock Register Bit
0 = Enable write to FEEMCR register
1 = Disable write to FEEMCR register
FEE32MCR/FEE28MCR — Flash EEPROM Module Configuration Register
Bit 7
6
5
4
3
2
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
$00F5/$00F9
1
Bit 0
0
BOOTP
0
1
This register controls the operation of the Flash EEPROM array. BOOTP
cannot be changed when the LOCK control bit in the FEELCK register is
set or if HVEN or PGM or ERAS in the FEECTL register is set .
BOOTP — Boot Protect
The boot blocks are located at $6000–$7FFF and $E000–$FFFF for
each Flash EEPROM module.
0 = Enable erase and program of 8K byte boot block
1 = Disable erase and program of 8K byte boot block
FEE32CTL/FEE28CTL — Flash EEPROM Control Register
$00F7/$00FB
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
FEESWAI HVEN
0
ERAS
PGM
RESET:
0
0
0
0
0
0
0
0
This register controls the programming and erasure of the Flash
EEPROM.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Flash Memory
Technical Data
99