MC912D60ACPVE8 Datasheet, PDF (365/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
ATD Registers
RES10 — A/D Resolution Select
0 = 8-bit resolution selected
1 = 10-bit resolution selected
This bit determines the resolution of the A/D converter: 8-bits or 10-
bits. The A/D converter has the accuracy of a 10-bit converter.
However, if low resolution is adequate, the conversion can be
speeded up by selecting 8-bit resolution.
SMP[1:0] — Sample Time Select
These two bits select the length of the third phase of the sample
period (in internal ATD clock cycles) which occurs after the buffered
sample and transfer. During this phase, the external analog signal is
connected directly to the storage node for final charging and improved
accuracy. Note that the ATD clock period is itself a function of the
prescaler value (bits PRS0–4). Table 18-4 lists the lengths available
for the third sample phase.
Table 18-4. Final Sample Time Selection
SMP1
0
0
1
1
SMP0
0
1
0
1
Final Sample Time
2 A/D clock periods
4 A/D clock periods
8 A/D clock periods
16 A/D clock periods
PRS[4:0] — ATD Clock Prescaler
The binary prescaler value (0 to 31) plus one (1 to 32) becomes the
divide-by-factor for a modulus counter used to prescale the system
PCLK frequency. The resulting scaled clock is further divided by 2
before the ATD internal clock is generated. This clock is used to drive
the S/H and A/D machines.
Note that the maximum ATD clock frequency is half of the system
clock. The default prescaler value is 00001 which results in a default
ATD clock frequency that is quarter of the system clock i.e. with 8MHz
bus the ATD module clock is 2MHz. Table 18-5 illustrates the divide-
by operation and the appropriate range of system clock frequencies.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Analog-to-Digital Converter
Technical Data
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