MC912D60ACPVE8 Datasheet, PDF (402/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

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Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
RESET:
0
0
0
0
0
0
BRKDH — Breakpoint Data Register, High Byte
1
Bit 0
9
Bit 8
0
0
$0024
These bits are compared to the most significant byte of the data bus or
the most significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the
breakpoint comparison.
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
BRKDL — Breakpoint Data Register, Low Byte
$0025
These bits are compared to the least significant byte of the data bus or
the least significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be
used in the breakpoint comparison.
19.6 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be
reconstructed in real time or from trace history that was captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution has already
begun by the time an operation is visible outside the MCU. A separate
instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO signal shares a pin with the LSTRB signal, and the
Technical Data
402
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MC68HC912D60A — Rev. 3.1
Freescale Semiconductor