MC912D60ACPVE8 Datasheet, PDF (445/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

23.7 PLL
Appendix: Information on MC68HC912D60A Mask Set Changes
PLL
The limp Home clock frequency has been re-alligned to the specification
values to reduce sensitivity to system noise and hence reduce PLL jitter.
Note: It is advisable to verify the XFC filter components and PLL lock
time due to the above changes.
VCO start-up will now be at the minimum frequency whilst the power up
sequence of the current controlled oscillator has been improved.
The XFC pin is now preconditioned to VDDPLL when PLL is deselected
so XFC doesn’t float. This ensures the PLL starts up at low frequency
and ramps up to the desired frequency.
MC68HC912D60A — Rev. 3.1
Freescale SemiconductorAppendix: Information on MC68HC912D60A Mask Set Changes
Technical Data
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