MC912D60ACPVE8 Datasheet, PDF (374/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
18.9.6 ATDTEST Module Test Register (ATDTEST)
The test registers implement various special (test) modes used to test
the ATD module. The reset bit in ATDTEST1 is always read/write. The
SAR (successive approximation register) can always be read but only
written in special (test) mode.
The functions implemented by the test registers are reserved for factory
test.
ATD0TESTH/ATD1TESTH — ATD Test Register
RESET:
Bit 7
SAR9
0
6
SAR8
0
5
SAR7
0
4
SAR6
0
3
SAR5
0
2
SAR4
0
1
SAR3
0
$0068/$01E8
Bit 0
SAR2
0
ATD0TESTL/ATD1TESTL — ATD Test Register
$0069/$01E9
Bit 7
6
5
4
3
2
1
Bit 0
SAR1
SAR0
RST
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
SAR[9:0] — Successive Approximation Register
This ten bit value represents the contents of the AD machine’s
successive approximation register. This value can always be read. It
can only be written in special (test) mode. Note that ATDTEST0 acts
as a ten bit register since the entire SAR is read/written when
accessing this address.
RST — Test Mode Reset Bit
0 = No reset
1 = Reset the ATD module
When set, this bit causes the ATD module to reset itself. This sets all
registers to their reset state (note the reset state of the reset bit is
zero), the current conversion and conversion sequence are aborted,
pending interrupts are cleared, and the module is placed in an idle
mode.
Technical Data
374
Analog-to-Digital Converter
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor