MC912D60ACPVE8 Datasheet, PDF (244/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
PAEN — Pulse Accumulator A System Enable
0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and
PAC2 can be enabled when their related enable bits in
ICPACR ($A8) are set.
Pulse Accumulator Input Edge Flag (PAIF) function is
disabled.
1 = Pulse Accumulator A system enabled. The two 8-bit pulse
accumulators PAC3 and PAC2 are cascaded to form the
PACA 16-bit pulse accumulator. When PACA in enabled, the
PACN3 and PACN2 registers contents are respectively the
high and low byte of the PACA.
PA3EN and PA2EN control bits in ICPACR ($A8) have no
effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled.
PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
PAMOD — Pulse Accumulator Mode
0 = event counter mode
1 = gated time accumulation mode
PEDGE — Pulse Accumulator Edge Control
For PAMOD bit = 0 (event counter mode).
0 = falling edges on PT7 pin cause the count to be incremented
1 = rising edges on PT7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 = PT7 input pin high enables M divided by 64 clock to Pulse
Accumulator and the trailing falling edge on PT7 sets the PAIF
flag.
1 = PT7 input pin low enables M divided by 64 clock to Pulse
Accumulator and the trailing rising edge on PT7 sets the PAIF
flag.
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Pin Action
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
Technical Data
244
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor