MC912D60ACPVE8 Datasheet, PDF (442/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Appendix: Changes from MC68HC912D60
To ensure compatibility, the application should not rely on ongoing
conversions being aborted. Also any interrupts from the completion of an
ongoing sequence should be masked and/or handled correctly.
22.2.7.7 SCF bit
In SCAN mode (SCAN bit = 1 in ATDxCTL5) the Sequence Complete
Flag (SCF bit in ATDSTATx) is set after completion of each conversion
sequence. Previously it was only set at the end of the first conversion
sequence.
To ensure compatibility the application should not rely on this flag being
set only once per SCAN mode.
22.2.7.8 ATDTESTx
Reading the ATDTESTx register in nornal modes returns the value of the
Successive Approximation Register (SAR). Previously it always read as
zero.
The RST bit in the ATDTESTx register can be written in normal modes
(in order to reset the ATD). Previously it was read only.
To ensure compatibility this register should not be read or written to.
Technical Data
442
Appendix: Changes from MC68HC912D60
MC68HC912D60A — Rev. 3.1
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