MC912D60ACPVE8 Datasheet, PDF (356/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
18.6.2 WAIT Mode
If the ASWAI control bit in ATDCTL2 is set, then the ATD responds to
WAIT mode. If the ASWAI control bit is clear, then the ATD ignores the
WAIT signal. The ATD response to the wait mode is to power down the
module. In this mode, the MCU does not have access to the control,
status or result registers.
18.6.3 Background Debug (ATD FREEZE) Mode
When debugging an application, it is useful to have the ATD pause when
a breakpoint is encountered. To accommodate this, there are two
FREEZE bits in the ATDCTL3 register used to select one of three
responses:
1. The ATD module may ignore the freeze request.
2. It may respond to the freeze request by finishing the current
conversion and ‘freezing’ before starting the next sample period.
3. It may respond by immediately ‘freezing’.
Control and timing logic is static allowing the register contents and timing
position to be remembered indefinitely. The analog electronics remains
powered up; however, internal leakage may compromise the accuracy
of a frozen conversion depending on the length of the freeze period.
When the BDM signal is negated clock activity resumes.
Access to the ATD register file is possible during the ‘frozen’ period.
18.6.4 Module Reset
The ATD module is reset on two different events.
1. In the case of a system reset.
2. If the RST bit in the ATDTEST register is activated.
The single difference between the two events is that the RST bit event
does not reset the ADPU bit to its reset state value - i.e. the module is
not reset into a powered down state and will be returned to an idle state.
Technical Data
356
Analog-to-Digital Converter
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor