MC912D60ACPVE8 Datasheet, PDF (230/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
14.3 Enhanced Capture Timer Modes of Operation
The Enhanced Capture Timer has 8 Input Capture, Output Compare
(IC/OC) channels same as on the HC12 standard timer (timer channels
TC0 to TC7). When channels are selected as input capture by selecting
the IOSx bit in TIOS register, they are called Input Capture (IC)
channels.
Four IC channels are the same as on the standard timer with one capture
register which memorizes the timer value captured by an action on the
associated input pin.
Four other IC channels, in addition to the capture register, have also one
buffer called holding register. This permits to memorize two different
timer values without generation of any interrupt.
Four 8-bit pulse accumulators are associated with the four buffered IC
channels. Each pulse accumulator has a holding register to memorize
their value by an action on its external input. Each pair of pulse
accumulators can be used as a 16-bit pulse accumulator.
The 16-bit modulus down-counter can control the transfer of the IC
registers contents and the pulse accumulators to the respective holding
registers for a given period, every time the count reaches zero.
The modulus down-counter can also be used as a stand-alone time base
with periodic interrupt capability.
14.3.1 IC Channels
The IC channels are composed of four standard IC registers and four
buffered IC channels.
An IC register is empty when it has been read or latched into the
holding register.
A holding register is empty when it has been read.
Technical Data
230
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor