MC912D60ACPVE8 Datasheet, PDF (123/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

9.5 Interrupt Control and Priority Registers
Resets and Interrupts
Interrupt Control and Priority Registers
Bit 7
6
5
4
3
2
1
Bit 0
IRQE
IRQEN
DLY
0
0
0
0
0
RESET:
0
1
1
0
0
0
0
0
INTCR — Interrupt Control Register
$001E
IRQE — IRQ Select Edge Sensitive Only
0 = IRQ configured for low-level recognition.
1 = IRQ configured to respond only to falling edges (on pin
PE1/IRQ).
IRQE can be read anytime and written once in normal modes. In
special modes, IRQE can be read anytime and written anytime,
except the first write is ignored.
IRQEN — External IRQ Enable
The IRQ pin has an active pull-up. See Table 3-4.
0 = External IRQ pin is disconnected from interrupt logic.
1 = External IRQ pin is connected to interrupt logic.
IRQEN can be read and written anytime in all modes.
DLY — Enable Oscillator Start-up Delay on Exit from STOP
The delay time of about 4096 cycles is based on the X clock rate
chosen.
0 = No stabilization delay imposed on exit from STOP mode. A
stable external oscillator must be supplied.
1 = Stabilization delay is imposed before processing resumes after
STOP.
DLY can be read anytime and written once in normal modes. In
special modes, DLY can be read and written anytime.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Resets and Interrupts
Technical Data
123