MC912D60ACPVE8 Datasheet, PDF (301/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Freescale Interconnect Bus
SCI0/MI Bus registers
Table 16-1. MI Bus Delay
MDL1
0
0
1
1
MDL0
0
1
0
1
Delay factor _{Delay time}⁽¹⁾
1
1.5625 µs⁽²⁾
2
3.125 µs
3
4.6875 µs
4
6.25 µs
1. 20kHz bit rate requires 25µs (40kHz) time slots.
2. 25µs ÷ 16
RAF — Receiver Active Flag
0 = A character is not being received
1 = A character is being received
Bit 7
6
5
R7/T7
R6/T6
R5/T5
Pull field
0
1
0
Push field
A2
A1
A0
RESET:
—
—
—
SC0DRL— MI Bus Data Register Low
4
R4/T4
1
D4
—
3
R3/T3
S1
D3
—
2
R2/T2
S2
D2
—
1
R1/T1
S3
D1
—
Bit 0
R0/T0
1
D0
—
$00C7
This register forms the 8-bit data/address word for the MI push field
and contains the 3-bit data word received as the MI pull field.
R7T7–R0T0 — Receive/Transmit Data Bits 7 to 0
READ: Reads access the three bits of pull field data (stored in bits
3–1) of the read-only MI Bus receive data register. Bits [7:4, 0] are a
fixed data pattern when a valid status and end-of-frame is returned. A
valid status is represented by the following data pattern: 0101 xxx1
(bits 7–0), where ‘xxx’ is the status. All ones in the receive data
register indicate that an error occurred on the MI Bus. Bits are
received LSB first by the MCU, and the status bits map as shown in
the above table.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Freescale Interconnect Bus
Technical Data
301