MC912D60ACPVE8 Datasheet, PDF (277/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MCU P CLOCK
(SAME AS E RATE)
DIVIDER
÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256
SELECT
SP0BR SPI BAUD RATE REGISTER
SPI CONTROL
Multiple Serial Interface
Serial Peripheral Interface (SPI)
8-BIT SHIFT REGISTER
READ DATA BUFFER
SP0DR SPI DATA REGISTER
SHIFT CONTROL LOGIC
LSBF
MSTR
SPE
CLOCK
CLOCK
LOGIC
SWOM
S
M
M
S
PIN
CONTROL
LOGIC
S
M
MISO
PS4
MOSI
PS5
SCK
PS6
SS
PS7
SPI
INTERRUPT
REQUEST
SP0SR SPI STATUS REGISTER
SP0CR1 SPI CONTROL REGISTER 1 SP0CR2 SPI CONTROL REGISTER 2
INTERNAL BUS
Figure 15-3. Serial Peripheral Interface Block Diagram
A clock phase control bit (CPHA) and a clock polarity control bit (CPOL)
in the SP0CR1 register select one of four possible clock formats to be
used by the SPI system. The CPOL bit simply selects non-inverted or
inverted clock. The CPHA bit is used to accommodate two
fundamentally different protocols by shifting the clock by one half cycle
or no phase shift.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Multiple Serial Interface
Technical Data
277