MC912D60ACPVE8 Datasheet, PDF (366/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
Table 18-5. Clock Prescaler Values
Prescale
Value
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
1xxxx
Total Divisor
÷2
÷4
÷6
÷8
÷10
÷12
÷14
÷16
Max PCLK⁽¹⁾
4 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
Do Not Use
Min PCLK⁽²⁾
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
1. Maximum conversion frequency is 2 MHz. Maximum PCLK divisor value will become
maximum conversion rate that can be used on this ATD module.
2. Minimum conversion frequency is 500 kHz. Minimum PCLK divisor value will become
minimum conversion rate that this ATD can perform.
18.9.4 ATDCTL5 ATD Control Register 5
ATD control register 5 determines the type of conversion sequence and
the analog input channels sampled. All writes to this register have an
immediate effect. If a conversion is in progress, the entire conversion
sequence is aborted. A write to this register (or ATDCTL4) initiates a new
conversion sequence (SCF and CCF bits are reset).
ATD0CTL5/ATD1CTL5 — ATD Control Register 5
$0065/$01E5
Bit 7
6
5
4
3
2
1
Bit 0
0
S8C
SCAN
MULT
SC
CC
CB
CA
RESET:
0
0
0
0
0
0
0
0
S8C / S1C — Conversion Sequence Length
S8C: Bit Position: 6, ATDCTL5
S1C: Bit Position: 3, ATDCTL3
The S8C/S1C bits define the length of a conversion sequence. Table
18-6 lists the coding combinations.
Technical Data
366
Analog-to-Digital Converter
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor