MC912D60ACPVE8 Datasheet, PDF (354/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
programmable constant in order to generate the ATD module’s internal
clock. One additional benefit of the prescaled clock feature is that it
allows the user further control over the sample period (note that
changing the module clock also affects conversion time).
The prescaler is based on a 5 bit modulus counter and divides the PCLK
by an integer value between 1 and 32. The final clock frequency is
obtained with a further division by 2.
The internal ATD module clock and the system PCLK have a direct
phase relationship, however the ATD module operates as if it is
effectively asynchronous to MCU bus clock cycles.
18.5 ATD Operational Modes
18.5.1 Power Down Mode
The ATD module can be powered down under program control. This is
done by turning the clock signals off to the digital electronics of the
module and eliminating the quiescent current draw of the analog
electronics.
Power down control is implemented in one of three ways.
1. Using the ADPU bit in control register ATDCTL2.
2. When STOP instruction is executed, the module will power down
for the duration of the STOP function.
3. If the module WAIT enable bit (ASWAI) is set and a WAIT
instruction is executed, the module will power down for the
duration of the WAIT function.
Note that the reset default for the ADPU bit is zero. Therefore, when this
module is reset, it is reset into the power down state.
Once the command to power down has been received, the ATD module
aborts any conversion sequence in progress and enters lower power
mode. When the module is powered up again, the bias settings in the
analog electronics must be given time to stabilize before conversions
Technical Data
354
Analog-to-Digital Converter
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor