MC912D60ACPVE8 Datasheet, PDF (132/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

I/O Ports with Key Wake-up
Bit 7
6
5
4
3
WI2CE KWIEG6 KWIEG5 KWIEG4 KWIEG3
RESET:
0
0
0
0
0
KWIEG — Key Wake-up Port G Interrupt Enable Register
2
KWIEG2
0
1
KWIEG1
0
Bit 0
KWIEG0
0
$002C
Read and write anytime.
WI2CE — Wake-up I²C Enable
0 = PG6 default key wake-up on falling edge
1 = I²C Start condition detection on PG7 and PG6
When WI2CE is set, PG6 and PG7 operate in wired-OR or open-drain
mode.
The I²C Start condition is defined as a high to low transition of the
SDA line when SCL is high. When WI2CE is set, a falling edge on
PG6 (SDA) is recognized only if PG7 (SCL) is high.
Depending on WI2CE bit, KWIEG6 enables either falling edge or I²C
Start condition interrupt.
KWIEG[6:0] — Key Wake-up Port G Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
Bit 7
6
5
4
3
KWIEH7 KWIEH6 KWIEH5 KWIEH4 KWIEH3
RESET:
0
0
0
0
0
KWIEH — Key Wake-up Port H Interrupt Enable Register
2
KWIEH2
0
1
KWIEH1
0
Bit 0
KWIEH0
0
Read and write anytime.
KWIEH[7:0] — Key Wake-up Port H Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
$002D
Technical Data
132
I/O Ports with Key Wake-up
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor