MC912D60ACPVE8 Datasheet, PDF (51/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pinout and Signal Descriptions
Signal Descriptions
Table 3-2. MC68HC912D60A Signal Description Summary
Pin Name
ADDR[7:0]
DATA[7:0]
ADDR[15:8]
DATA[15:8]
DBE
ECLK
CAL
CGMTST
MODB/
IPIPE1,
MODA/
IPIPE0
ECLK
LSTRB/
TAGLO
R/W
IRQ
XIRQ
SMODN/BK
GD/TAGHI
PW[3:0]
SS
SCK
Pin Number
80-pin 112-pin
23–16
31–24
48–41
64–57
25
36
25
36
25
36
26
37
26, 27
37, 38
28
39
37
53
38
54
39
55
40
56
15
23
80, 1–3 112, 1–3
70
96
69
95
Description
External bus pins share function with general-purpose I/O ports A and B.
In single chip modes, the pins can be used for I/O. In expanded modes,
the pins are used for the external buses.
Data bus control and, in expanded mode, enables the drive control of
external buses during external reads.
Inverted ECLK used to latch the address.
CAL is the output of the Slow Mode programmable clock divider, SLWCLK,
and is used as a calibration reference for functions such as time of day. It
is overridden when DBE function is enabled. It always has a 50% duty
cycle.
Clock generation module test output.
State of mode select pins during reset determine the initial operating mode
of the MCU. After reset, MODB and MODA can be configured as
instruction queue tracking signals IPIPE1 and IPIPE0 or as general-
purpose I/O pins.
E Clock is the output connection for the external bus clock. ECLK is used
as a timing reference and for address demultiplexing.
Low byte strobe (0 = low byte valid), in all modes this pin can be used as
I/O. The low strobe function is the exclusive-NOR of A0 and the internal
SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin
function TAGLO used in instruction tagging. See Development Support.
Indicates direction of data on expansion bus. Shares function with general-
purpose I/O. Read/write in expanded modes.
Maskable interrupt request input provides a means of applying
asynchronous interrupt requests to the MCU. Either falling edge-
sensitive triggering or level-sensitive triggering is program selectable
(INTCR register).
Provides a means of requesting asynchronous nonmaskable interrupt
requests after reset initialization
Single-wire background interface pin is dedicated to the background
debug function. During reset, this pin determines special or normal
operating mode. Pin function TAGHI used in instruction tagging. See
Development Support.
Pulse Width Modulator channel outputs.
Slave select output for SPI master mode, input for slave mode or master
mode.
Serial clock for SPI system.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Pinout and Signal Descriptions
Technical Data
51