MC912D60ACPVE8 Datasheet, PDF (98/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Flash Memory
7.3 Overview
The Flash EEPROM array is arranged in a 16-bit configuration and may
be read as either bytes, aligned words or misaligned words. Access time
is one bus cycle for byte and aligned word access and two bus cycles for
misaligned word operations.
The Flash EEPROM module supports bulk erase only.
Each Flash EEPROM module has hardware interlocks which protect
stored data from accidental corruption. An erase- and program-
protected 8-Kbyte block for boot routines is located at $6000–$7FFF or
$E000–$FFFF depending upon the mapped location of the Flash
EEPROM arrays.
On 1L02H and later mask sets, an optional protection scheme is
supported to protect the entire two Flash EEPROM modules (32-Kbyte
and 28-Kbyte) against accident program or erase. This is achieved using
the protection bit FPOPEN in EEPROM EEMCR (see 7.11 Flash
protection bit FPOPEN).
7.4 Flash EEPROM Control Block
A 4-byte register block for each module controls the Flash EEPROM
operation. Configuration information is specified and programmed
independently from the contents of the Flash EEPROM array.
After reset, the control register block for the 32K Flash EEPROM array
(FEE32) is located from addresses $00F4 to $00F7 and for the 28K
Flash EEPROM array (FEE28) from $00F8 to $00FB.
7.5 Flash EEPROM Arrays
After reset, the 32K Flash EEPROM array is located from addresses
$8000 to $FFFF and the 28K Flash EEPROM array is from $1000 to
$7FFF. In expanded modes, the Flash EEPROM arrays are turned off.
The Flash EEPROM can be mapped to an alternate address range. See
Operating Modes and Resource Mapping.
Technical Data
98
Flash Memory
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor