MC912D60ACPVE8 Datasheet, PDF (133/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

I/O Ports with Key Wake-up
Key Wake-up and Port Registers
Bit 7
6
5
4
0
KWIFG6 KWIFG5 KWIFG4
RESET:
0
0
0
0
KWIFG — Key Wake-up Port G Flag Register
3
KWIFG3
0
2
KWIFG2
0
1
KWIFG1
0
Bit 0
KWIFG0
0
$002E
Each flag, except bit 6, is set by a falling edge on its associated input pin.
To clear the flag, write one to the corresponding bit in KWIFG.
Read and write anytime
Bit 7 always reads zero.
KWIFG6 — Key Wake-up Port G Flag 6
0 = Falling edge on the associated bit or I2C Start condition has not
occurred
1 = Falling edge on the associated bit or I2C Start condition has
occurred (an interrupt will occur if the associated enable bit is set)
Depending on WI2CE bit in KWIEG register, KWIFG6 flags either
falling edge or I2C Start condition.
KWIFG[5:0] — Key Wake-up Port G Flags
0 = Falling edge on the associated bit has not occurred
1 = Falling edge on the associated bit has occurred (an interrupt
will occur if the associated enable bit is set).
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
I/O Ports with Key Wake-up
Technical Data
133