MC912D60ACPVE8 Datasheet, PDF (364/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
Finally, which result registers hold valid data can be tracked using the
conversion complete flags. Fast flag clear mode may or may not be
useful in a particular application to track valid data.
FRZ1, FRZ0 — Background Debug Freeze Enable
Background debug freeze function allows the ATD module to pause
when a breakpoint is encountered. Table 18-3 shows how FRZ1 and
FRZ0 determine the ATD’s response to a breakpoint. When BDM is
deasserted, the ATD module continues operating as it was before the
breakpoint occurred.
Table 18-3. ATD Response to Background Debug Enable
FRZ1
0
0
1
1
FRZ0
0
1
0
1
ATD Response
Continue conversions in active background mode
Reserved
Finish current conversion, then freeze
Freeze when BDM is active
18.9.3 ATDCTL4 ATD Control Register 4
ATD control register 4 is used to select the internal ATD clock frequency
(based on the system clock), select the length of the third phase of the
sample period, and set the resolution of the A/D conversion (i.e. 8-bits or
10-bits). All writes to this register have an immediate effect. If a
conversion is in progress, the entire conversion sequence is aborted. A
write to this register (or ATDCTL5) initiates a new conversion sequence.
ATD0CTL4/ATD1CTL4 — ATD Control Register 4
RESET:
Bit 7
RES10
0
6
SMP1
0
5
SMP0
0
4
PRS4
0
3
PRS3
0
2
PRS2
0
1
PRS1
0
$0064/$01E4
Bit 0
PRS0
1
Technical Data
364
Analog-to-Digital Converter
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor