MC912D60ACPVE8 Datasheet, PDF (88/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Bus Control and Input/Output
Bit 7
6
Single Chip PB7
PB6
RESET:
—
—
Expanded ADDR7/ ADDR6/
& Periph: DATA7 DATA6
Expanded ADDR7
narrow
ADDR6
PORTB — Port B Register
5
PB5
—
ADDR5/
DATA5
ADDR5
4
PB4
—
ADDR4/
DATA4
ADDR4
3
PB3
—
ADDR3/
DATA3
ADDR3
2
PB2
—
ADDR2/
DATA2
ADDR2
1
PB1
—
ADDR1/
DATA1
ADDR1
Bit 0
PB0
—
ADDR0/
DATA0
ADDR0
$0001
Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0]
(except in narrow mode) respectively. When this port is not used for
external addresses such as in single-chip mode, these pins can be used
as general-purpose I/O. DDRB determines the primary direction of each
pin. This register is not in the on-chip map in expanded and peripheral
modes. Read and write anytime.
Bit 7
6
5
DDB7
DDB6
DDB5
RESET:
0
0
0
DDRB — Port B Data Direction Register
4
DDB4
0
3
DDB3
0
2
DDB2
0
1
DDB1
0
Bit 0
DDB0
0
$0003
This register determines the primary direction for each port B pin when
functioning as a general-purpose I/O port. DDRB is not in the on-chip
map in expanded and peripheral modes. Read and write anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
Technical Data
88
Bus Control and Input/Output
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor