MC912D60ACPVE8 Datasheet, PDF (209/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pulse Width Modulator
Introduction
CLOCK SOURCE
(ECLK or Scaled ECLK)
GATE
(CLOCK EDGE SYNC)
PWENx
SYNC
PPOL = 1
PPOL = 0
PWDTY
PWCNTx
CENTR = 1
RESET
(DUTY CYCLE)
8-BIT COMPARE =
PWDTYx
(PERIOD)
8-BIT COMPARE =
PWPERx
FROM PORT P
DATA REGISTER
T
Q _MUX
Q
PPOLx
MUX
TO PIN
DRIVER
(PWPER − PWDTY) × 2
PWPER × 2
PWDTY
Figure 13-2. Block Diagram of PWM Center-Aligned Output Channel
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Pulse Width Modulator
Technical Data
209