MC912D60ACPVE8 Datasheet, PDF (52/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pinout and Signal Descriptions
Table 3-2. MC68HC912D60A Signal Description Summary
Pin Name
Pin Number
80-pin 112-pin
Description
SDO/MOSI 68
94
Master out/slave in pin for serial peripheral interface
SDI/MISO
67
93
Master in/slave out pin for serial peripheral interface
TxD1
66
92
SCI1 transmit pin
RxD1
65
91
SCI1 receive pin
TxD0
64
90
SCI0 transmit pin
RxD0
63
89
SCI0 receive pin
IOC[7:0]
14–11,
7–4
18–15, 7–4
Pins used for input capture and output compare in the timer and pulse
accumulator subsystem.
AN1[7:0]
N/A
84/82/80/78/
76/74/72/70
Analog
inputs
for the
analog-to-digital conversion
module
1
AN0[7:0]
60–53
83/81/79/77/
75/73/71/69
Analog
inputs
for the
analog-to-digital conversion
module
0
TEST
71
97
Used for factory test purposes. Do not connect in the application; may be
bonded to 5.5 V max.
TxCAN
72
104 MSCAN transmit pin. Leave unconnected if MSCAN is not used.
RxCAN
73
105
MSCAN receive pin. Pin has internal pull-up; where msCAN module is not
used, do not tie to VSS.
KWG[6:0]
8 (KWG4
only)
9–11, 19–22
Key wake-up and general purpose I/O; can cause an interrupt when an
input transitions from high to low. On 80-pin QFP all 8 I/O should be
initialised.
PGUPD
(1)
13
Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.
KWH[7:0]
24 (KWH4
only)
32–35,
49–52
Key wake-up and general purpose I/O; can cause an interrupt when an
input transitions from high to low. On 80-pin QFP all 8 I/O should be
initialised.
PHUPD
(2)
41
Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.
1. In the 80-pin version PGUPD is connected internally to VDD
2. In the 80-pin version PHUPD is connected internally to VSS
3.6 Port Signals
The MC68HC912D60A incorporates eight ports which are used to
control and access the various device subsystems. When not used for
these purposes, port pins may be used for general-purpose I/O. In
addition to the pins described below, each port consists of a data register
Technical Data
52
Pinout and Signal Descriptions
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor