MC912D60ACPVE8 Datasheet, PDF (129/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Technical Data — MC68HC912D60A
Section 10. I/O Ports with Key Wake-up
10.1 Contents
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.3 Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . . 130
10.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.2 Introduction
The 112QFP MC68HC912D60A offers 16 additional I/O port pins with
key wake-up capability on 15 of them (KWG7 is used for I²C start
detect). Only two (KWG4 and KWH4) are available on the 80QFP
package. All Port G and Port H pins should either be defined as outputs
or have their pull-ups/downs enabled.
The key wake-up feature of the MC68HC912D60A issues an interrupt
that will wake up the CPU when it is in the STOP or WAIT mode. Two
ports are associated with the key wake-up function: port G and port H.
Port G and port H wake-ups are triggered with a falling signal edge. For
each pin which has an interrupt enabled, there is a path to the interrupt
request signal which has no clocked devices when the part is in stop
mode. This allows an active edge to bring the part out of stop.
Digital filtering is included to prevent pulses shorter than a specified
value from waking the part from STOP.
An interrupt is generated when a bit in the KWIFG or KWIFH register and
its corresponding KWIEG or KWIEH bit are both set. All 15 bits/pins
share the same interrupt vector. Key wake-ups can be used with the pins
configured as inputs or outputs.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
I/O Ports with Key Wake-up
Technical Data
129