MC912D60ACPVE8 Datasheet, PDF (108/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

EEPROM Memory
A steady internal self-time clock is required to provide accurate counts
to meet EEPROM program/erase requirements. This clock is generated
via a programmable 10-bit prescaler register. Automatic program/erase
termination is also provided.
In ordinary situations, with crystal operating properly, the steady internal
self-time clock is derived from the input clock source (EXTALi). The
divider value is as in EEDIVH:EEDIVL. In limp-home mode, where the
oscillator clock has malfunctioned or is unavailable, the self-time clock is
derived from the PLL at a nominal f_VCOMIN using a predefined divider
value of $0023. Program/erase operation is not guaranteed in limp-
home mode.
CAUTION:
It is strongly recommended that program/erase operation is terminated
in the event of loss of crystal, either by the application software (clearing
EEPGM & EELAT bits) when entering limp home mode or by enabling
the clock monitor to generate a clock monitor reset. This will prevent
unnecessary stress on the emulated EEPROM during oscillator failure.
8.5 EEPROM Control Registers
EEDIVH — EEPROM Modulus Divider
$00EE
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
EEDIV9 EEDIV8
RESET:
0
0
0
0
0
0
—⁽¹⁾
—⁽¹⁾
1. Loaded from SHADOW word.
EEDIVL — EEPROM Modulus Divider
RESET:
Bit 7
EEDIV7
—⁽¹⁾
6
EEDIV6
—⁽¹⁾
5
EEDIV5
—⁽¹⁾
1. Loaded from SHADOW word.
4
EEDIV4
—⁽¹⁾
3
EEDIV3
—⁽¹⁾
2
EEDIV2
—⁽¹⁾
1
EEDIV1
—⁽¹⁾
Bit 0
EEDIV0
—⁽¹⁾
$00EF
Technical Data
108
EEPROM Memory
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor