MC912D60ACPVE8 Datasheet, PDF (343/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
Programmer’s Model of Control Registers
17.13.12 msCAN12 Transmit Error Counter (CTXERR)
Bit 7
CTXERR R TXERR7
$010F W
RESET
0
6
TXERR6
0
5
TXERR5
0
4
TXERR4
0
3
TXERR3
0
2
TXERR2
0
1
TXERR1
0
Bit 0
TXERR0
0
This register reflects the status of the msCAN12 transmit error counter.
The register is read only.
NOTE: Both error counters must only be read when in SLEEP or SOFT_RESET
mode.
17.13.13 msCAN12 Identifier Acceptance Registers (CIDAR0–7)
On reception each message is written into the background receive
buffer. The CPU is only signalled to read the message however, if it
passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message is overwritten by the next
message (dropped).
The acceptance registers of the msCAN12 are applied on the IDR0 to
IDR3 registers of incoming messages in a bit by bit manner.
For extended identifiers all four acceptance and mask registers are
applied. For standard identifiers only the first two (CIDMR0/1 and
CIDAR0/1) are applied.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
MSCAN Controller
Technical Data
343