MC912D60ACPVE8 Datasheet, PDF (90/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Bus Control and Input/Output
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
PE[1:0] are associated with XIRQ and IRQ and cannot be configured as
outputs. These pins can be read regardless of whether the alternate
interrupt functions are enabled.
This register is not in the map in peripheral mode and expanded modes
while the EME control bit is set.
Read and write anytime.
RESET:
BIT 7
NDBE
0
6
CGMTE
0
5
PIPOE
0
4
NECLK
0
3
LSTRE
0
2
RDWE
0
RESET:
0
0
1
0
1
1
RESET:
1
1
0
1
0
0
RESET:
1
0
0
1
0
0
RESET:
0
0
1
0
1
1
PEAR — Port E Assignment Register
1
CALE
0
0
0
0
0
BIT 0
DBENE
0
Normal
Expanded
0
Special
Expanded
0
Peripheral
0
Normal
single chip
0
Special
single chip
$000A
The PEAR register is used to choose between the general-purpose I/O
functions and the alternate bus control functions of port E. When an
alternate control function is selected, the associated DDRE bits are
overridden.
The reset condition of this register depends on the mode of operation
because bus-control signals are needed immediately after reset in some
modes.
In normal single-chip mode, no external bus control signals are needed
so all of port E is configured for general-purpose I/O.
Technical Data
90
Bus Control and Input/Output
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor