MC912D60ACPVE8 Datasheet, PDF (283/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
Serial Peripheral Interface (SPI)
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
SPR2
SPR1
SPR0
RESET:
0
0
0
0
0
0
0
0
SP0BR — SPI Baud Rate Register
$00D2
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
These bits are used to specify the SPI clock rate.
Table 15-4. SPI Clock Rate Selection
SPR2 SPR1 SPR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
E Clock
Divisor
2
4
8
16
32
64
128
256
Frequency at Frequency at
E Clock = 4 MHz E Clock = 8 MHz
2.0 MHz
4.0 MHz
1.0 MHz
2.0 MHz
500 kHz
1.0 MHz
250 kHz
500 KHz
125 kHz
250 KHz
62.5 kHz
125 KHz
31.3 kHz
62.5 KHz
15.6 kHz
31.3 KHz
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
WCOL
0
MODF
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
SP0SR — SPI Status Register
$00D3
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
SPIF is set after the eighth SCK cycle in a data transfer and it is
cleared by reading the SP0SR register (with SPIF set) followed by an
access (read or write) to the SPI data register.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Multiple Serial Interface
Technical Data
283