MC912D60ACPVE8 Datasheet, PDF (226/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
M clock
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
÷1, 2, ..., 128
Prescaler
16-bit Free-running
16 BIT MAmINaiTnIMtimEeRr
M clock
÷ 1, 4, 8, 16
Prescaler
Pin logic
Pin logic
Pin logic
Pin logic
Delay counter _EDG0
Delay counter _EDG1
Delay counter _EDG2
Delay counter _EDG3
Comparator
TC0 capture/compare register
TC0H hold register
Comparator
TC1 capture/compare register
TC1H hold register
Comparator
TC2 capture/compare register
TC2H hold register
Comparator
TC3 capture/compare register
TC3H hold register
16-bit load register
16-bit modulus
down counter
0 ^RESET
PAC0
PA0H hold register
0 ^RESET
PAC1
PA1H hold register
0 ^RESET
PAC2
PA2H hold register
0 ^RESET
PAC3
PA3H hold register
Pin logic
EDG4
EDG0
MUX
Comparator
TC4 capture/compare register
LATQ, BUFEN
(queue mode)
Pin logic
EDG5
EDG1
MUX
Pin logic
EDG6
EDG2
MUX
Comparator
TC5 capture/compare register
Comparator
TC6 capture/compare register
Read TC3H
hold register
Read TC2H
hold register
Read TC1H
hold register
Pin logic
EDG7
EDG3
MUX
Comparator
TC7 capture/compare register
Read TC0H
hold register
Figure 14-2. Timer Block Diagram in Queue Mode
Technical Data
226
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor