MC912D60ACPVE8 Datasheet, PDF (182/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Oscillator
12.4.1.2 Internal Parasitic Reduction
Any oscillator circuit’s gain margin is reduced when a low AC-impedance
(low resistance or high capacitance) is placed in parallel with the
resonator. In the Colpitts oscillator configuration, this impedance is
dominated by the parasitic capacitance from the EXTAL pin to VSS.
Since this capacitance is large compared to the shunt capacitance of the
resonator, the gain margin in a Colpitts configuration is less than in other
configurations.
To remedy this issue, the internal circuits were optimized for lower
capacitance. This should increase the gain margin and allow more
robust operation over process, temperature and voltage variation. To
maximize the benefit of this change, different external component values
are required. However, the oscillator will function at least as well as the
MC68HC912D60A version with the same components.
12.4.1.3 Bias Current Process Optimization
For proper oscillation, the gain margin of the oscillator must exceed one
or the circuit will not oscillate. Due to the sensitive gain margin of the
Colpitts configuration, process variance in the bias current (which
controls the gain of the amplifier) can cause the gain margin to be much
lower than typical. This can be as a result of either too much or too little
current.
To reduce the process sensitivity of the gain, the material of the device
that sets the bias current was changed to a material with tighter process
and temperature control. As a result, the transconductance and Ibias
variances are more limited than in the previous design.
Technical Data
182
Oscillator
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor