MC912D60ACPVE8 Datasheet, PDF (333/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
Programmer’s Model of Control Registers
17.13.4 msCAN12 Bus Timing Register 0 (CBTR0)
CBTR0 R
$0102 W
RESET
Bit 7
SJW1
0
6
SJW0
0
5
BRP5
0
4
BRP4
0
3
BRP3
0
2
BRP2
0
1
BRP1
0
Bit 0
BRP0
0
SJW1, SJW0 — Synchronization Jump Width
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 17-5).
Table 17-5. Synchronization jump width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization jump width
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
BRP5 – BRP0 — Baud Rate Prescaler
These bits determine the time quanta (Tq) clock, which is used to
build up the individual bit timing, according to Table 17-6.
BRP5
0
0
0
0
:
:
1
Table 17-6. Baud rate prescaler
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler value
(P)
1
2
3
4
:
:
64
NOTE: The CBTR0 register can only be written if the SFTRES bit in CMCR0 is
set.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
MSCAN Controller
Technical Data
333