MC912D60ACPVE8 Datasheet, PDF (121/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Resets and Interrupts
Latching of Interrupts
9.4 Latching of Interrupts
XIRQ is always level triggered and IRQ can be selected as a level
triggered interrupt. These level triggered interrupt pins should only be
released during the appropriate interrupt service routine. Generally the
interrupt service routine will handshake with the interrupting logic to
release the pin. In this way, the MCU will start the interrupt service
sequence only to determine that there is no longer an interrupt source.
In the event that this does not occur, the trap vector will be taken.
If IRQ is selected as an edge triggered interrupt, the hold time of the level
after the active edge is independent of when the interrupt is serviced. As
long as the minimum hold time is met, the interrupt will be latched inside
the MCU. In this case the IRQ edge interrupt latch is cleared
automatically when the interrupt is serviced.
All of the remaining interrupts are latched by the MCU with a flag bit.
These interrupt flags should be cleared during an interrupt service
routine or when interrupts are masked by the I bit. By doing this, the
MCU will never get an unknown interrupt source and take the trap vector.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Resets and Interrupts
Technical Data
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