MC912D60ACPVE8 Datasheet, PDF (260/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC0H — Timer Input Capture Holding Register 0
1
Bit 0
9
Bit 8
1
Bit 0
$00B8–$00B9
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC1H — Timer Input Capture Holding Register 1
1
Bit 0
9
Bit 8
1
Bit 0
$00BA–$00BB
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC2H — Timer Input Capture Holding Register 2
1
Bit 0
9
Bit 8
1
Bit 0
$00BC–$00BD
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC3H — Timer Input Capture Holding Register 3
1
Bit 0
9
Bit 8
1
Bit 0
$00BE–$00BF
Read: any time
Write: has no effect.
These registers are used to latch the value of the input capture registers
TC0 – TC3. The corresponding IOSx bits in TIOS ($80) should be
cleared (see IC Channels).
Technical Data
260
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor