MC912D60ACPVE8 Datasheet, PDF (119/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Technical Data — MC68HC912D60A
Section 9. Resets and Interrupts
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.3 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.4 Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.5 Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . . 123
9.6 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.7 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.8 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.9 Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.2 Introduction
CPU12 exceptions include resets and interrupts. Each exception has an
associated 16-bit vector, which points to the memory location where the
routine that handles the exception is located. Vectors are stored in the
upper 128 bytes of the standard 64K byte address map.
The six highest vector addresses are used for resets and non-maskable
interrupt sources. The remainder of the vectors are used for maskable
interrupts, and all must be initialized to point to the address of the
appropriate service routine.
9.2.1 Exception Priority
A hardware priority hierarchy determines which reset or interrupt is
serviced first when simultaneous requests are made. Six sources are not
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Resets and Interrupts
Technical Data
119