MC912D60ACPVE8 Datasheet, PDF (206/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Oscillator
12.5.4 MC68HC912D60P Guidelines
Proper and robust operation of the oscillator circuit requires excellent
board layout design practice. Poor layout of the application board can
contribute to EMC susceptibility, noise generation, slow starting
oscillators, and reaction to noise on the clock input buffer. In addition to
published errata for the MC68HC912D60A, the following guidelines
must be followed or failure in operation may occur.
• Minimize Capacitance between EXTAL and XTAL traces —
The Pierce oscillator architecture is sensitive to capacitance in
parallel with the resonator (from EXTAL to XTAL). To reduce this
capacitance, run a shield trace (connected to VSS) between
EXTAL and XTAL as far as possible.
• Shield all oscillator components from all noisy traces. If the
VSS used for shielding is not identical to the oscillator reference,
it must be considered a noisy signal.
• Keep the VSSPLL pin and the VSS reference to the oscillator
as identical as possible. Impedance between these signals must
be minimum.
• Observe best practice supply bypassing on all MCU power
pins. The oscillator’s supply reference is VDD, not VDDPLL.
• Account for XTAL–VSS and EXTAL–VSS parasitics in
component values. The specified component values assume a
maximum parasitic capacitance of 1pF for these pins.
NOTE:
An increase in the EXTAL–VSS or XTAL–VSS parasitic as a result of
reducing EXTAL–XTAL parasitic is acceptable provided the component
values are reduced by the appropriate value.
• Minimize XTAL and EXTAL routing lengths to reduce EMC
issues.
NOTE:
EXTAL and XTAL routing resistances are less important than
capacitances. Using minimum width traces is an acceptable trade-off to
reduce capacitance.
Technical Data
206
Oscillator
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor