MC912D60ACPVE8 Datasheet, PDF (281/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
Serial Peripheral Interface (SPI)
SPIE — SPI Interrupt Enable
0 = SPI interrupts are inhibited
1 = Hardware interrupt sequence is requested each time the SPIF
or MODF status flag is set
SPE — SPI System Enable
0 = SPI internal hardware is initialized and SPI system is in a low-
power disabled state.
1 = PS[4:7] are dedicated to the SPI function
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
SWOM — Port S Wired-OR Mode
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
outputs
MSTR — SPI Master/Slave Mode Select
0 = Slave mode
1 = Master mode
CPOL, CPHA — SPI Clock Polarity, Clock Phase
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See Figure 15-4 and Figure 15-5.
SSOE — Slave Select Output Enable
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDS7.
LSBF — SPI LSB First enable
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Multiple Serial Interface
Technical Data
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