MC912D60ACPVE8 Datasheet, PDF (217/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pulse Width Modulator
PWM Register Description
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT0 Bit 7
6
5
4
3
2
1
Bit 0
$0048
PWCNT1 Bit 7
6
5
4
3
2
1
Bit 0
$0049
PWCNT2 Bit 7
6
5
4
3
2
1
Bit 0
$004A
PWCNT3 Bit 7
6
5
4
3
2
1
Bit 0
$004B
RESET:
0
0
0
0
0
0
0
0
PWCNTx — PWM Channel Counters
Read and write anytime. A write will cause the PWM counter to reset to
$00.
In special mode, if DISCR = 1, a write does not reset the PWM counter.
The PWM counters are not reset when PWM channels are disabled. The
counters must be reset prior to a new enable.
Each counter may be read any time without affecting the count or the
operation of the corresponding PWM channel. Writes to a counter cause
the counter to be reset to $00 and force an immediate load of both duty
and period registers with new values. To avoid a truncated PWM period,
write to a counter while the counter is disabled. In left-aligned output
mode, resetting the counter and starting the waveform output is
controlled by a match between the period register and the value in the
counter. In center-aligned output mode the counters operate as up/down
counters, where a match in period changes the counter direction. The
duty register changes the state of the output during the period to
determine the duty.
When a channel is enabled, the associated PWM counter starts at the
count in the PWCNTx register using the clock selected for that channel.
In special mode, when DISCP = 1 and configured for left-aligned output,
a match of period does not reset the associated PWM counter.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Pulse Width Modulator
Technical Data
217